C5P Board Configuration

C5P Board Configuration

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Copyright © 2003-2017 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLOCK_50_B3B T13 input 1.5 V
CLOCK_50_B4A U12 input 1.5 V
CLOCK_50_B5B R20 input 3.3-V LVTTL
CLOCK_50_B6A N20 input 3.3-V LVTTL
CLOCK_50_B7A H12 input 3.3-V LVTTL
CLOCK_50_B8A N9 input 3.3-V LVTTL

Buttons
Name Location Direction IO Standard
CPU_RESET_n AB24 input 3.3-V LVTTL
KEY[0] M21 input 3.3-V LVTTL
KEY[1] K25 input 3.3-V LVTTL
KEY[2] K26 input 3.3-V LVTTL
KEY[3] G26 input 3.3-V LVTTL

Swtiches
Name Location Direction IO Standard
SW[0] G20 input 3.3-V LVTTL
SW[1] F21 input 3.3-V LVTTL
SW[2] E21 input 3.3-V LVTTL
SW[3] H19 input 3.3-V LVTTL

LED
Name Location Direction IO Standard
LED[0] U20 output 3.3-V LVTTL
LED[1] T19 output 3.3-V LVTTL
LED[2] Y24 output 3.3-V LVTTL
LED[3] Y23 output 3.3-V LVTTL

HEX0
Name Location Direction IO Standard
HEX0_DP AA6 output 3.3-V LVTTL
HEX0[0] T8 output 3.3-V LVTTL
HEX0[1] P26 output 3.3-V LVTTL
HEX0[2] V8 output 3.3-V LVTTL
HEX0[3] U7 output 3.3-V LVTTL
HEX0[4] U25 output 3.3-V LVTTL
HEX0[5] W8 output 3.3-V LVTTL
HEX0[6] U26 output 3.3-V LVTTL

HEX1
Name Location Direction IO Standard
HEX1_DP V25 output 3.3-V LVTTL
HEX1[0] T7 output 3.3-V LVTTL
HEX1[1] W20 output 3.3-V LVTTL
HEX1[2] AB6 output 3.3-V LVTTL
HEX1[3] AC22 output 3.3-V LVTTL
HEX1[4] Y9 output 3.3-V LVTTL
HEX1[5] W21 output 3.3-V LVTTL
HEX1[6] N25 output 3.3-V LVTTL

FAN
Name Location Direction IO Standard
FAN_CTRL AD7 output 3.3-V LVTTL

DRAM
Name Location Direction IO Standard
DRAM_CLK F26 output 3.3-V LVTTL
DRAM_CKE E25 output 3.3-V LVTTL
DRAM_ADDR[0] D26 output 3.3-V LVTTL
DRAM_ADDR[1] H20 output 3.3-V LVTTL
DRAM_ADDR[2] F23 output 3.3-V LVTTL
DRAM_ADDR[3] G22 output 3.3-V LVTTL
DRAM_ADDR[4] B25 output 3.3-V LVTTL
DRAM_ADDR[5] D22 output 3.3-V LVTTL
DRAM_ADDR[6] C25 output 3.3-V LVTTL
DRAM_ADDR[7] E23 output 3.3-V LVTTL
DRAM_ADDR[8] B26 output 3.3-V LVTTL
DRAM_ADDR[9] E24 output 3.3-V LVTTL
DRAM_ADDR[10] D25 output 3.3-V LVTTL
DRAM_ADDR[11] M26 output 3.3-V LVTTL
DRAM_ADDR[12] M25 output 3.3-V LVTTL
DRAM_BA[0] J20 output 3.3-V LVTTL
DRAM_BA[1] H22 output 3.3-V LVTTL
DRAM_DQ[0] L24 inout 3.3-V LVTTL
DRAM_DQ[1] M24 inout 3.3-V LVTTL
DRAM_DQ[2] N23 inout 3.3-V LVTTL
DRAM_DQ[3] K23 inout 3.3-V LVTTL
DRAM_DQ[4] H24 inout 3.3-V LVTTL
DRAM_DQ[5] J23 inout 3.3-V LVTTL
DRAM_DQ[6] K24 inout 3.3-V LVTTL
DRAM_DQ[7] L22 inout 3.3-V LVTTL
DRAM_DQ[8] G25 inout 3.3-V LVTTL
DRAM_DQ[9] G24 inout 3.3-V LVTTL
DRAM_DQ[10] H25 inout 3.3-V LVTTL
DRAM_DQ[11] J21 inout 3.3-V LVTTL
DRAM_DQ[12] L23 inout 3.3-V LVTTL
DRAM_DQ[13] K21 inout 3.3-V LVTTL
DRAM_DQ[14] N24 inout 3.3-V LVTTL
DRAM_DQ[15] M22 inout 3.3-V LVTTL
DRAM_LDQM H23 output 3.3-V LVTTL
DRAM_UDQM F24 output 3.3-V LVTTL
DRAM_CS_n F22 output 3.3-V LVTTL
DRAM_WE_n J25 output 3.3-V LVTTL
DRAM_CAS_n J26 output 3.3-V LVTTL
DRAM_RAS_n E26 output 3.3-V LVTTL

DDR3
Name Location Direction IO Standard
DDR3_ADDR[0] AE6 output SSTL-15 Class I
DDR3_ADDR[1] AF6 output SSTL-15 Class I
DDR3_ADDR[2] AF7 output SSTL-15 Class I
DDR3_ADDR[3] AF8 output SSTL-15 Class I
DDR3_ADDR[4] U10 output SSTL-15 Class I
DDR3_ADDR[5] U11 output SSTL-15 Class I
DDR3_ADDR[6] AE9 output SSTL-15 Class I
DDR3_ADDR[7] AF9 output SSTL-15 Class I
DDR3_ADDR[8] AB12 output SSTL-15 Class I
DDR3_ADDR[9] AB11 output SSTL-15 Class I
DDR3_ADDR[10] AC9 output SSTL-15 Class I
DDR3_ADDR[11] AC8 output SSTL-15 Class I
DDR3_ADDR[12] AB10 output SSTL-15 Class I
DDR3_ADDR[13] AC10 output SSTL-15 Class I
DDR3_ADDR[14] W11 output SSTL-15 Class I
DDR3_BA[0] V10 output SSTL-15 Class I
DDR3_BA[1] AD8 output SSTL-15 Class I
DDR3_BA[2] AE8 output SSTL-15 Class I
DDR3_CK_p N10 output Differential 1.5-V SSTL Class I
DDR3_CK_n P10 output Differential 1.5-V SSTL Class I
DDR3_CKE AF14 output SSTL-15 Class I
DDR3_DQS_p[0] V13 inout Differential 1.5-V SSTL Class I
DDR3_DQS_p[1] U14 inout Differential 1.5-V SSTL Class I
DDR3_DQS_p[2] V15 inout Differential 1.5-V SSTL Class I
DDR3_DQS_p[3] W16 inout Differential 1.5-V SSTL Class I
DDR3_DQS_n[0] W13 inout Differential 1.5-V SSTL Class I
DDR3_DQS_n[1] V14 inout Differential 1.5-V SSTL Class I
DDR3_DQS_n[2] W15 inout Differential 1.5-V SSTL Class I
DDR3_DQS_n[3] W17 inout Differential 1.5-V SSTL Class I
DDR3_DQ[0] AA14 inout SSTL-15 Class I
DDR3_DQ[1] Y14 inout SSTL-15 Class I
DDR3_DQ[2] AD11 inout SSTL-15 Class I
DDR3_DQ[3] AD12 inout SSTL-15 Class I
DDR3_DQ[4] Y13 inout SSTL-15 Class I
DDR3_DQ[5] W12 inout SSTL-15 Class I
DDR3_DQ[6] AD10 inout SSTL-15 Class I
DDR3_DQ[7] AF12 inout SSTL-15 Class I
DDR3_DQ[8] AC15 inout SSTL-15 Class I
DDR3_DQ[9] AB15 inout SSTL-15 Class I
DDR3_DQ[10] AC14 inout SSTL-15 Class I
DDR3_DQ[11] AF13 inout SSTL-15 Class I
DDR3_DQ[12] AB16 inout SSTL-15 Class I
DDR3_DQ[13] AA16 inout SSTL-15 Class I
DDR3_DQ[14] AE14 inout SSTL-15 Class I
DDR3_DQ[15] AF18 inout SSTL-15 Class I
DDR3_DQ[16] AD16 inout SSTL-15 Class I
DDR3_DQ[17] AD17 inout SSTL-15 Class I
DDR3_DQ[18] AC18 inout SSTL-15 Class I
DDR3_DQ[19] AF19 inout SSTL-15 Class I
DDR3_DQ[20] AC17 inout SSTL-15 Class I
DDR3_DQ[21] AB17 inout SSTL-15 Class I
DDR3_DQ[22] AF21 inout SSTL-15 Class I
DDR3_DQ[23] AE21 inout SSTL-15 Class I
DDR3_DQ[24] AE15 inout SSTL-15 Class I
DDR3_DQ[25] AE16 inout SSTL-15 Class I
DDR3_DQ[26] AC20 inout SSTL-15 Class I
DDR3_DQ[27] AD21 inout SSTL-15 Class I
DDR3_DQ[28] AF16 inout SSTL-15 Class I
DDR3_DQ[29] AF17 inout SSTL-15 Class I
DDR3_DQ[30] AD23 inout SSTL-15 Class I
DDR3_DQ[31] AF23 inout SSTL-15 Class I
DDR3_DM[0] AF11 output SSTL-15 Class I
DDR3_DM[1] AE18 output SSTL-15 Class I
DDR3_DM[2] AE20 output SSTL-15 Class I
DDR3_DM[3] AE24 output SSTL-15 Class I
DDR3_CS_n R11 output SSTL-15 Class I
DDR3_WE_n T9 output SSTL-15 Class I
DDR3_CAS_n W10 output SSTL-15 Class I
DDR3_RAS_n Y10 output SSTL-15 Class I
DDR3_RESET_n AE19 output SSTL-15 Class I
DDR3_ODT AD13 output SSTL-15 Class I
DDR3_RZQ AE11 input 1.5 V

Uart to Usb
Name Location Direction IO Standard
UART_TX P21 output 3.3-V LVTTL
UART_RX P22 input 3.3-V LVTTL
UART_CTS W25 input 3.3-V LVTTL
UART_RTS W26 output 3.3-V LVTTL

GPIO
Name Location Direction IO Standard
GPIO_0[0] G15 inout 3.3-V LVTTL
GPIO_0[1] C9 inout 3.3-V LVTTL
GPIO_0[2] G14 inout 3.3-V LVTTL
GPIO_0[3] B9 inout 3.3-V LVTTL
GPIO_0[4] B24 inout 3.3-V LVTTL
GPIO_0[5] D10 inout 3.3-V LVTTL
GPIO_0[6] A24 inout 3.3-V LVTTL
GPIO_0[7] C10 inout 3.3-V LVTTL
GPIO_0[8] G16 inout 3.3-V LVTTL
GPIO_0[9] H13 inout 3.3-V LVTTL
GPIO_0[10] C14 inout 3.3-V LVTTL
GPIO_0[11] B15 inout 3.3-V LVTTL
GPIO_0[12] D15 inout 3.3-V LVTTL
GPIO_0[13] C15 inout 3.3-V LVTTL
GPIO_0[14] D21 inout 3.3-V LVTTL
GPIO_0[15] A19 inout 3.3-V LVTTL
GPIO_0[16] D20 inout 3.3-V LVTTL
GPIO_0[17] A18 inout 3.3-V LVTTL
GPIO_0[18] E20 inout 3.3-V LVTTL
GPIO_0[19] B22 inout 3.3-V LVTTL
GPIO_0[20] E19 inout 3.3-V LVTTL
GPIO_0[21] A21 inout 3.3-V LVTTL
GPIO_0[22] E18 inout 3.3-V LVTTL
GPIO_0[23] C23 inout 3.3-V LVTTL
GPIO_0[24] F18 inout 3.3-V LVTTL
GPIO_0[25] C22 inout 3.3-V LVTTL
GPIO_0[26] H14 inout 3.3-V LVTTL
GPIO_0[27] G17 inout 3.3-V LVTTL
GPIO_0[28] J12 inout 3.3-V LVTTL
GPIO_0[29] C20 inout 3.3-V LVTTL
GPIO_0[30] J11 inout 3.3-V LVTTL
GPIO_0[31] B19 inout 3.3-V LVTTL
GPIO_0[32] N12 inout 3.3-V LVTTL
GPIO_0[33] C17 inout 3.3-V LVTTL
GPIO_0[34] M12 inout 3.3-V LVTTL
GPIO_0[35] B17 inout 3.3-V LVTTL
GPIO_1[0] L8 inout 3.3-V LVTTL
GPIO_1[1] A7 inout 3.3-V LVTTL
GPIO_1[2] K9 inout 3.3-V LVTTL
GPIO_1[3] B7 inout 3.3-V LVTTL
GPIO_1[4] L7 inout 3.3-V LVTTL
GPIO_1[5] A5 inout 3.3-V LVTTL
GPIO_1[6] K6 inout 3.3-V LVTTL
GPIO_1[7] B6 inout 3.3-V LVTTL
GPIO_1[8] M9 inout 3.3-V LVTTL
GPIO_1[9] L9 inout 3.3-V LVTTL
GPIO_1[10] K8 inout 3.3-V LVTTL
GPIO_1[11] D6 inout 3.3-V LVTTL
GPIO_1[12] J8 inout 3.3-V LVTTL
GPIO_1[13] E6 inout 3.3-V LVTTL
GPIO_1[14] H8 inout 3.3-V LVTTL
GPIO_1[15] G7 inout 3.3-V LVTTL
GPIO_1[16] H9 inout 3.3-V LVTTL
GPIO_1[17] F7 inout 3.3-V LVTTL
GPIO_1[18] H10 inout 3.3-V LVTTL
GPIO_1[19] A12 inout 3.3-V LVTTL
GPIO_1[20] G10 inout 3.3-V LVTTL
GPIO_1[21] B11 inout 3.3-V LVTTL
GPIO_1[22] M11 inout 3.3-V LVTTL
GPIO_1[23] B12 inout 3.3-V LVTTL
GPIO_1[24] L11 inout 3.3-V LVTTL
GPIO_1[25] A13 inout 3.3-V LVTTL
GPIO_1[26] A17 inout 3.3-V LVTTL
GPIO_1[27] A16 inout 3.3-V LVTTL
GPIO_1[28] E13 inout 3.3-V LVTTL
GPIO_1[29] C13 inout 3.3-V LVTTL
GPIO_1[30] D13 inout 3.3-V LVTTL
GPIO_1[31] C12 inout 3.3-V LVTTL
GPIO_1[32] G12 inout 3.3-V LVTTL
GPIO_1[33] H7 inout 3.3-V LVTTL
GPIO_1[34] F12 inout 3.3-V LVTTL
GPIO_1[35] J7 inout 3.3-V LVTTL

Arduino Interface
Name Location Direction IO Standard
ADC_SCK R26 output 3.3-V LVTTL
ADC_SDO AB26 input 3.3-V LVTTL
ADC_SDI AA26 output 3.3-V LVTTL
ADC_CONVST T26 output 3.3-V LVTTL
ARD_IO[0] Y26 inout 3.3-V LVTTL
ARD_IO[1] V23 inout 3.3-V LVTTL
ARD_IO[2] V24 inout 3.3-V LVTTL
ARD_IO[3] U24 inout 3.3-V LVTTL
ARD_IO[4] T24 inout 3.3-V LVTTL
ARD_IO[5] T23 inout 3.3-V LVTTL
ARD_IO[6] T22 inout 3.3-V LVTTL
ARD_IO[7] R24 inout 3.3-V LVTTL
ARD_IO[8] P20 inout 3.3-V LVTTL
ARD_IO[9] R23 inout 3.3-V LVTTL
ARD_IO[10] R25 inout 3.3-V LVTTL
ARD_IO[11] P23 inout 3.3-V LVTTL
ARD_IO[12] AC25 inout 3.3-V LVTTL
ARD_IO[13] AD25 inout 3.3-V LVTTL
ARD_IO[14] AB25 inout 3.3-V LVTTL
ARD_IO[15] AA24 inout 3.3-V LVTTL

PCIE
Name Location Direction IO Standard
PCIE_SMBCLK R10 inout 3.3-V LVTTL
PCIE_SMBDAT AA7 inout 3.3-V LVTTL
PCIE_REFCLK_p V6 input HCSL
PCIE_TX_p[0] AE4 output 1.5-V PCML
PCIE_TX_p[1] AC4 output 1.5-V PCML
PCIE_TX_p[2] AA4 output 1.5-V PCML
PCIE_TX_p[3] W4 output 1.5-V PCML
PCIE_RX_p[0] AD2 input 1.5-V PCML
PCIE_RX_p[1] AB2 input 1.5-V PCML
PCIE_RX_p[2] Y2 input 1.5-V PCML
PCIE_RX_p[3] V2 input 1.5-V PCML
PCIE_PERST_n U22 inout 3.3-V LVTTL
PCIE_WAKE_n Y8 inout 3.3-V LVTTL

SMA
Name Location Direction IO Standard
SMA_CLKIN T21 input 3.3-V LVTTL
SMA_CLKOUT Y25 output 3.3-V LVTTL